@article{Kim2025, 
author = {Mookyum Kim and Ji Cheol Byen and Doyeon Kim and Rakesh S. Sharbidre and Prashant Narute and Min-Seok Kim and Seong-Gu Hong},
title = {High-performance trench-structured thin film transistor with a micropatterned double-layer oxide semiconductor of varying thickness},
year = {2025},
journal = {Nano Research},
volume = {18},
number = {1},
pages = {94907065},
keywords = {thin film transistor, trench structure, oxide semiconductor, current-driving capabilities, switching properties, scalable fabrication},
url = {https://www.sciopen.com/article/10.26599/NR.2025.94907065},
doi = {10.26599/NR.2025.94907065},
abstract = {Amorphous oxide semiconductor thin film transistors (TFTs) are essential for next-generation high-resolution displays due to their superior electrical properties, stability, and compatibility with flexible substrates. This paper reports a novel TFT architecture featuring a trench-structured oxide semiconductor layer of varying thickness and a corresponding fabrication process, offering excellent current-driving capabilities, switching characteristics, and wafer-scale producibility compared to planar-structured TFTs and previous trench-structured TFTs (TS-TFTs). Our approach forms trenches through micropatterning the first oxide semiconductor layer deposited on the substrate, followed by the deposition of the second oxide semiconductor layer using an atomic layer deposition supercycle method. This process introduces a trench structure, comprising a micropatterned double-layer oxide semiconductor with a thin active segment and thick amplifier segments, between source and drain electrodes. This configuration allows for precise dimensional control of the active segment, facilitating an optimized TFT architecture design. The developed TS-TFTs exhibit excellent electrical properties, including a field-effect mobility of 87.84 cm2·V−1·s−1, a subthreshold swing of 0.074 V·dec−1, near-zero threshold voltage, negligible hysteresis, and a threshold voltage shift of 0.4 V under positive bias stress over 3600 s. Furthermore, an electrical performance analysis of 16 TS-TFTs fabricated on a 4-inch wafer shows that their transfer curves are almost coincident, demonstrating the feasibility of the proposed fabrication process for wafer-scale production.}
}