@article{Zeng2026, 
author = {Zhaoquan Zeng and Martin Mallinson and Liang He and Emily Slous and Lijiao Gong and Ning Zhang},
title = {A Low-Cost Open-Loop Fractional Output Divider for Audio System-on-Chip in 180 nm CMOS},
year = {2026},
journal = {Tsinghua Science and Technology},
volume = {31},
number = {2},
pages = {1031-1043},
keywords = {fractional output divider, digital-to-frequency converter, jitter filter, audio system-on-chip, ∆-Σ modulation},
url = {https://www.sciopen.com/article/10.26599/TST.2024.9010162},
doi = {10.26599/TST.2024.9010162},
abstract = {This paper introduces a  Δ−Σ fractional output divider (FOD) designed for audio system-on-chip (SoC) applications with low design and implementation cost. In contrast to conventional FOD design methodologies that utilize a multi-modulus divider (MMD) or a multi-phase multiplexer (MPM) based divider incorporating complex jitter filters, the proposed FOD adopts a feed-forward architecture employing simple circuit building blocks. It leverages a  Δ−Σ digital-to-frequency converter (DFC) to generate fractionally synthesized output frequencies, eliminating the synchronous constraint associated with MMD and MPM methods. The DFC employs a fully-synthesizable  Δ−Σ modulator and resistor-2 resistor (R-2R) digital-to-analog converter to generate 4-level waveform patterns containing the desired output frequency information. These patterns are then processed through an integrator and a zero-crossing detector to reconstruct the fractionally divided output clock signal. Furthermore, to minimize jitter, a simple edge combiner-based jitter filter is cascaded with the DFC output. Implemented in 180 nm digital complementary metal-oxide-semiconductor process and operating at 1.2 V supply voltage, the proposed FOD offers an output frequency range of 500 kHz to 45 MHz, with  Nmin=FIN/FOUT=4. Specifically, It divides a 26 MHz input to generate a 6.144 MHz (128fs = 128 × 44.1 kHz) output, exhibiting a root-mean-square jitter of 3.68 ps, while consuming 0.22 mW of power.}
}