@article{Dang2022, 
author = {Weiqi Dang and Bei Zhao and Chang Liu and Xiangdong Yang and Lingan Kong and Zheyi Lu and Bo Li and Jia Li and Hongmei Zhang and Wanying Li and Shun Shi and Ziyue Qin and Lei Liao and Xidong Duan and Yuan Liu},
title = {Ultimate dielectric scaling of 2D transistors via van der Waals metal integration},
year = {2022},
journal = {Nano Research},
volume = {15},
number = {2},
pages = {1603-1608},
keywords = {MoS2, van der Waals (vdW) integration, dielectric scaling, transfer gate, metal oxide semiconductor field effect transistor (MOSFET)},
url = {https://www.sciopen.com/article/10.1007/s12274-021-3708-1},
doi = {10.1007/s12274-021-3708-1},
abstract = {The two-dimensional transition metal dichalcogenides (TMDs) have attracted intense interest as an atomically thin semiconductor channel for the continued transistor scaling. However, with a dangling bond free surface, it has been a key challenge to reliably integrate high-quality gate dielectrics on TMDs. In particular, the atomic layer deposition of dielectrics on TMDs typically features highly non-uniform nucleation and produces a highly rough or porous dielectric film with rich pinholes that are prone to further damage during the gate integration process. Herein we report a van der Waals (vdW) integration route towards highly reliable gate metal integration on porous dielectrics. The physical lamination process employed by the vdW integration avoids the direct deposition of metal electrodes into porous dielectrics to ensure reliable gate integration and produce low gate leakage devices. The electrical measurements demonstrate the vdW integrated MoS2 top gate devices exhibit substantially reduced gate leakage current that is about 3–5 orders of magnitude smaller than that with deposited metal electrodes. Furthermore, we show the vdW integration process can be used to create high performance top-gated MoS2 transistors with ultrathin Al2O3 dielectrics down to 1 nm, representing the ultimate dielectric scaling for TMDs transistors. This study demonstrates that vdW integration can enable highly reliable gate integration on relatively low quality dielectrics on TMDs, and opens an interesting pathway to high-performance top-gate transistors using dangling bond free two-dimensional (2D) semiconductors.}
}