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We explore 10-nm wide Si nanowire (SiNW) field-effect transistors (FETs) for logic applications, via the fabrication and testing of SiNW-based ring oscillators. We report on SiNW surface treatments and dielectric annealing, for producing SiNW FETs that exhibit high performance in terms of large on/off-state current ratio (~108), low drain-induced barrier lowering (~30 mV) and low subthreshold swing (~80 mV/decade). The performance of inverter and ring-oscillator circuits fabricated from these nanowire FETs are also explored. The inverter demonstrates the highest voltage gain (~148) reported for a SiNW-based NOT gate, and the ring oscillator exhibits near rail-to-rail oscillation centered at 13.4 MHz. The static and dynamic characteristics of these NW devices indicate that these SiNW-based FET circuits are excellent candidates for various high-performance nanoelectronic applications.

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Publication history
Copyright
Acknowledgements

Publication history

Received: 11 May 2011
Revised: 07 June 2011
Accepted: 08 June 2011
Published: 24 June 2011
Issue date: October 2011

Copyright

© Tsinghua University Press and Springer-Verlag Berlin Heidelberg 2011

Acknowledgements

Acknowledgement

The authors acknowledge H. Ahmad and Y. -S. Shin for graphics assistance. This work was funded by the National Science Foundation under Grant CCF-0541461 and the Department of Energy (DE-FG02-04ER46175). D. Tham gratefully acknowledges support by the KAUST Scholar Award.

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