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Regular Paper

DIR: Dynamic Request Interleaving for Improving the Read Performance of Aged Solid-State Drives

Department of Computer Science and Technology, Xi’an Jiaotong University, Shaanxi 710049, China

A preliminary version of the paper was published in the Proceedings of NVMSA 2019.

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Abstract

Triple-level cell (TLC) NAND flash is increasingly adopted to build solid-state drives (SSDs) for modern computer systems. While TLC NAND flash effectively improves storage density, it faces severe reliability issues; in particular, the pages exhibit different raw bit error rates (RBERs). Integrating strong low-density parity-check (LDPC) code helps to improve reliability but suffers from prolonged and proportional read latency due to multiple read retries for worse pages. The straightforward idea is that dispersing page-size data across several pages in different types can achieve a lower average RBER and reduce the read latency. However, directly implementing this simple idea into flash translation layer (FTL) induces the read amplification issue as one logic page residing in more than one physical page brings several read operations. In this paper, we propose the Dynamic Request Interleaving (DIR) technology for improving the performance of TLC NAND flash-based SSDs, in particular, the aged ones with large RBERs. DIR exploits the observation that the latency of an I/O request is determined, without considering the queuing time, by the access of the slowest device page, i.e., the page that has the highest RBER. By grouping consecutive logical pages that have high locality and interleaving their encoded data in different types of device pages that have different RBERs, DIR effectively reduces the number of read retries for LDPC with limited read amplification. To meet the requirement of allocating hybrid page types for interleaved data, we also design a page-interleaving friendly page allocation scheme, which splits all the planes into multi-plane regions for storing the interleaved data and single-plane regions for storing the normal data. The pages in the multi-plane region can be read/written in parallel by the proposed multi-plane command and avoid the read amplification issue. Based on the DIR scheme and the proposed page allocation scheme, we build DIR-enable FTL, which integrates the proposed schemes into the FTL with some modifications. Our experimental results show that adopting DIR in aged SSDs exploits nearly 33% locality from I/O requests and, on average, reduces 43% read latency over conventional aged SSDs.

Keywords

performancetriple-layer cell solid-state drive (TLC SSD)interleaving dataunbalanced bit error rate

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References

[1]
Min C, Kim K, Cho H, Lee S W, Eom Y I. SFS: Random write considered harmful in solid state drives. In Proc. the 10th USENIX Conference on File and Storage Technologies, Feb. 2012, pp.1–16. DOI: 10.5555/2208461.2208473.
[2]

Matsui C, Sun C, Takeuchi K. Design of hybrid SSDs with storage class memory and NAND flash memory. Proceedings of the IEEE, 2017, 105(9): 1812–1821. DOI: 10.1109/JPROC.2017.2716958.
Crossref Google Scholar
[3]
Zhao K, Zhao W Z, Sun H B, Zhang T, Zhang X D, Zheng N N. LDPC-in-SSD: Making advanced error correction codes work effectively in solid state drives. In Proc. the 11th USENIX Conference on File and Storage Technologies, Feb. 2013, pp.243–256. DOI: 10.5555/2591272.2591298.
[4]
Elyasi N, Arjomand M, Sivasubramaniam A, Kandemir M T, Das C R, Jung M. Exploiting intra-request slack to improve SSD performance. In Proc. the 22nd International Conference on Architectural Support for Programming Languages and Operating Systems, Apr. 2017, pp.375–388. DOI: 10.1145/3037697.3037728.
Crossref
[5]

Cui J H, Zhang Y T, Wu W G, Yang J, Wang Y F, Huang J H. DLV: Exploiting device level latency variations for performance improvement on flash memory storage systems. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, 2018, 37(8): 1546–1559. DOI: 10.1109/TCAD.2017.2766156.
Crossref Google Scholar
[6]
Du Y J, Zou D Q, Li Q, Shi L, Jin H, Xue C J. LaLDPC: Latency-aware LDPC for read performance improvement of solid state drives. In Proc. the 33rd International Conference on Massive Storage Systems and Technology, May 2017, pp.1–11.
[7]
Wu F, Zhu Y, Xiong Q, Lu Z H, Zhou Y, Kong W Z, Xie C S. Characterizing 3D charge trap NAND flash: Observations, analyses and applications. In Proc. the 36th International Conference on Computer Design, Oct. 2018, pp.381–388. DOI: 10.1109/ICCD.2018.00064.
Crossref
[8]
Yaakobi E, Grupp L, Siegel P H, Swanson S, Wolf J K. Characterization and error-correcting codes for TLC flash memories. In Proc. the 2012 International Conference on Computing, Networking and Communications, Jan. 2012, pp.486–491. DOI: 10.1109/ICCNC.2012.6167470.
Crossref
[9]
Zhao W Z, Sun H B, Lv M J, Dong G Q, Zheng N N, Zhang T. Improving min-sum LDPC decoding throughput by exploiting intra-cell bit error characteristic in MLC NAND flash memory. In Proc. the 30th Symposium on Mass Storage Systems and Technologies, Jun. 2014, pp.1–6. DOI: 10.1109/MSST.2014.6855550.
Crossref
[10]
Nakamura T, Deguchi Y, Takeuchi K. AEP-LDPC ECC with error dispersion coding for burst error reduction of 2D and 3D NAND flash memories. In Proc. the 2017 IEEE International Memory Workshop, May 2017. DOI: 10.1109/IMW.2017.7939070.
Crossref
[11]
Nie S Q, Zhang Y T, Wu W G, Zhang C, Yang J. DIR: Dynamic request interleaving for improving the read performance of aged SSDs. In Proc. the 2019 IEEE Non-Volatile Memory Systems and Applications Symposium, Aug. 2019. DOI: 10.1109/NVMSA.2019.8863520.
Crossref
[12]
Gao C M, Shi L, Xue C J, Ji C, Yang J, Zhang Y T. Parallel all the time: Plane level parallelism exploration for high performance SSDs. In Proc. the 35th Symposium on Mass Storage Systems and Technologies, May 2019, pp.172–184. DOI: 10.1109/MSST.2019.000-5.
Crossref
[13]
Agrawal N, Prabhakaran V, Wobber T, Davis J D, Manasse M S, Panigrahy R. Design tradeoffs for SSD performance. In Proc. the 2008 USENIX Annual Technical Conference, Feb. 2008, pp.57–70.
[14]
Tavakkol A, Gómez-Luna J, Sadrosadati M, Ghose S, Mutlu O. MQSim: A framework for enabling realistic studies of modern multi-queue SSD devices. In Proc. the 16th USENIX Conference on File and Storage Technologies, Feb. 2018, pp.49–65.
[15]

Suh K D, Suh B H, Lim Y H, Kim J K, Choi Y J, Koh Y N, Lee S S, Kwon S C, Choi B S, Yum J S, Choi J H, Kim J R, Lim H K. A 3.3 V 32 Mb NAND flash memory with incremental step pulse programming scheme. IEEE Journal of Solid-State Circuits, 1995, 30(11): 1149–1156. DOI: 10.1109/4.475701.
Crossref Google Scholar
[16]
Micheloni R. 3D Flash Memories. Springer, 2016. DOI: 10.1007/978-94-017-7512-0.
Crossref
[17]
Hu Y, Jiang H, Feng D, Tian L, Luo H, Zhang S P. Performance impact and interplay of SSD parallelism through advanced commands, allocation strategy and data granularity. In Proc. the 2011 International Conference on Supercomputing, May 2011, pp.96–107. DOI: 10.1145/1995896.1995912.
Crossref
[18]

Kim M, Jung W, Lee H J, Chung E Y. A novel NAND flash memory architecture for maximally exploiting plane-level parallelism. IEEE Trans. Very Large Scale Integration (VLSI) Systems, 2019, 27(8): 1957–1961. DOI: 10.1109/TVLSI.2019.2905626.
Crossref Google Scholar
[19]
Khakifirooz A, Balasubrahmanyam S, Fastow R, Gaewsky K H, Ha C W, Haque R, Jungroth O W, Law S, Madraswala A S, Ngo B, Naveen Prabhu V, Rajwade S, Ramamurthi K, Shenoy R S, Snyder J, Sun C, Thimmegowda D, Pathak B M, Kalavade P. 30.2 A 1Tb 4b/cell 144-tier floating-gate 3D-NAND flash memory with 40MB/s program throughput and 13.8Gb/mm2 bit density. In Proc. the 2021 IEEE International Solid-State Circuits Conference, Feb. 2021, pp.424–426. DOI: 10.1109/ISSCC42613.2021.9365777.
Crossref
[20]

Shibata N, Kanda K, Shimizu T, Nakai J, Nagao O, Kobayashi N, Miakashi M, Nagadomi Y, Nakano T, Kawabe T, Shibuya T, Sako M, Yanagidaira K, Hashimoto T, Date H, Sato M, Nakagawa T, Musha J, Minamoto T, Uda M, Nakamura D, Sakurai K, Yamashita T, Zhou J Y, Tachibana R, Takagiwa T, Sugimoto T, Ogawa M, Ochi Y, Kawaguchi K, Kojima M, Ogawa T, Hashiguchi T, Fukuda R, Masuda M, Kawakami K, Someya T, Kajitani Y, Matsumoto Y, Sato J, Raghunathan N, Koh Y L, Chen S, Lee J, Nasu H, Sugawara H, Hosono K, Hisada T, Nakamura H. A 1.33-Tb 4-bit/cell 3-D flash memory on a 96-word-line-layer technology. IEEE Journal of Solid-State Circuits, 2020, 55(1): 178–188. DOI: 10.1109/JSSC. 2019.2941758.
Crossref Google Scholar
[21]
Kalavade P. 4 bits/cell 96 layer floating gate 3D NAND with CMOS under array technology and SSDs. In Proc. the 2020 IEEE International Memory Workshop, May 2020. DOI: 10.1109/IMW48823.2020.9108135.
Crossref
[22]

Narayanan D, Donnelly A, Rowstron A. Write off-loading: Practical power management for enterprise storage. ACM Trans. Storage, 2008, 4(3): Article No. 10. DOI: 10.1145/1416944.1416949.
Crossref Google Scholar
[23]
Narayanan D, Thereska E, Donnelly A, Elnikety S, Rowstron A. Migrating server storage to SSDs: Analysis of tradeoffs. In Proc. the 4th ACM European Conference on Computer Systems, Apr. 2009, pp.145–158. DOI: 10.1145/1519065.1519081.
Crossref
[24]
Park J, Jeong J, Lee S, Song Y, Kim J. Improving performance and lifetime of NAND storage systems using relaxed program sequence. In Proc. the 53rd Annual Design Automation Conference, Jun. 2016, Article No. 63. DOI: 10.1145/2897937.2898032.
Crossref
[25]
Parat K, Goda A. Scaling trends in NAND flash. In Proc. the 2018 IEEE International Electron Devices Meeting, Dec. 2018. DOI: 10.1109/IEDM.2018.8614694.
Crossref
[26]
Huh H, Cho W, Lee J, Noh Y, Park Y, Ok S, Kim J, Cho K, Lee H, Kim G, Park K, Kim K, Lee H, Chai S, Kwon C, Cho H, Jeong C, Yang Y J, Goo J, Park J, Lee J, Kirr H, Jo K, Park C, Nam H, Song H, Lee S, Jeong W, Ahn K O, Jung T S. 13.2 A 1Tb 4b/cell 96-stacked-WL 3D NAND flash memory with 30MB/s program throughput using peripheral circuit under memory cell array technique. In Proc. the 2020 IEEE International Solid-State Circuits Conference, Feb. 2020, pp.220–221. DOI: 10.1109/ISSCC19947.2020.9063117.
Crossref
[27]
Chen F, Hou B, Lee R. Internal parallelism of flash memory-based solid-state drives. ACM Transactions on Storage (TOS), 2016, 12(3): 1–39. DOI: 10.1145/2818376.
Crossref
[28]

Jung M, Zhang J, Abulila A, Kwon M, Shahidi N, Shalf J, Kim N S, Kandemir M. SimpleSSD: Modeling solid state drives for holistic system simulation. IEEE Computer Architecture Letters, 2018, 17(1): 37–41. DOI: 10.1109/LCA.2017.2750658.
Crossref Google Scholar
[29]
Abe M, Matsui C, Mizushina K, Suzuki S, Takeuchi K. Computational approximate storage with neural network-based error patrol of 3D-TLC NAND flash memory for machine learning applications. In Proc. the 2020 IEEE International Memory Workshop, May 2020. DOI: 10.1109/IMW48823.2020.9108136.
Crossref
[30]

Zhang M, Wu F, Chen X B, Du Y J, Liu W H, Zhao Y H, Wan J G, Xie C S. RBER aware multi-sensing for improving read performance of 3D MLC NAND flash memory. IEEE Access, 2018, 6: 61934–61947. DOI: 10.1109/ACCESS.2018.2873081.
Crossref Google Scholar
[31]

Wu F, Zhang M, Du Y J, Liu W H, Lu Z, Wan J G, Tan Z H, Xie C S. Using error modes aware LDPC to improve decoding performance of 3-D TLC NAND flash. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, 2020, 39(4): 909–921. DOI: 10.1109/TCAD.2019.2897706.
Crossref Google Scholar
[32]
Zhang M, Wu F, Du Y J, Yang C M, Xie C S, Wan J G. CooECC: A cooperative error correction scheme to reduce LDPC decoding latency in NAND flash. In Proc. the 2017 IEEE International Conference on Computer Design, Nov. 2017, pp.657–664. DOI: 10.1109/ICCD.2017.115.
Crossref
[33]
Cai Y, Yalcin G, Mutlu O, Haratsch E F, Cristal A, Unsal O S, Mai K. Flash correct-and-refresh: Retention-aware error management for increased flash memory lifetime. In Proc. the 30th IEEE International Conference on Computer Design, Sept. 2012, pp.94–101. DOI: 10.1109/ICCD.2012.6378623.
Crossref
[34]
Luo Y X, Cai Y, Ghose S, Choi J, Mutlu O. WARM: Improving NAND flash memory lifetime with write-hotness aware retention management. In Proc. the 31st Symposium on Mass Storage Systems and Technologies, May 30–Jun. 5, 2015, pp.1–14. DOI: 10.1109/MSST.2015.7208284.
Crossref
[35]
Li Q, Shi L, Gao C M, Wu K J, Xue C J, Zhuge Q F, Sha E H M. Maximizing IO performance via conflict reduction for flash memory storage systems. In Proc. the 2015 Design, Automation & Test in Europe Conference & Exhibition, Mar. 2015, pp.904–907. DOI: 10.5555/2755753.2757022.
Crossref
[36]
Tokutomi T, Tanakamaru S, Iwasaki T O, Takeuchi K. Advanced error prediction LDPC for high-speed reliable TLC NAND-based SSDs. In Proc. the 6th IEEE International Memory Workshop, May 2014. DOI: 10.1109/IMW.2014.6849375.
Crossref
[37]
Li Q, Shi L, Xue C J, Zhuge Q F, Sha E H M. Improving LDPC performance via asymmetric sensing level placement on flash memory. In Proc. the 22nd Asia and South Pacific Design Automation Conference, Jan. 2017, pp.560–565. DOI: 10.1109/ASPDAC.2017.7858383.
Crossref
[38]
Cai Y, Luo Y X, Haratsch E F, Mai K, Mutlu O. Data retention in MLC NAND flash memory: Characterization, optimization, and recovery. In Proc. the 21st International Symposium on High Performance Computer Architecture, Feb. 2015, pp.551–563. DOI: 10.1109/HPCA.2015.7056062.
Crossref
[39]

Peleato B, Agarwal R, Cioffi J M, Qin M H, Siegel P H. Adaptive read thresholds for NAND flash. IEEE Trans. Communications, 2015, 63(9): 3069–3081. DOI: 10.1109/TCOMM.2015.2453413.
Crossref Google Scholar
[40]
Zhang M, Wu F, He X B, Huang P, Wang S Z, Xie C S. REAL: A retention error aware LDPC decoding scheme to improve NAND flash read performance. In Proc. the 32nd Symposium on Mass Storage Systems and Technologies, May 2016. DOI: 10.1109/MSST.2016.7897085.
Crossref
[41]
Aslam C A, Guan Y L, Cai K. Retention-aware belief-propagation decoding for NAND flash memory. IEEE Trans. Circuits and Systems II: Express Briefs, 2017, 64(6): 725–729. DOI: 10.1109/TCSII.2016.2602359.
Crossref
Journal of Computer Science and Technology
Volume 39 Issue 1,
January 2024
Pages 82-98
DOI: 10.1007/s11390-023-1601-y
Cite this article:
Nie S-Q, Zhang C, Wu W-G. DIR: Dynamic Request Interleaving for Improving the Read Performance of Aged Solid-State Drives. Journal of Computer Science and Technology, 2024, 39(1): 82-98. https://doi.org/10.1007/s11390-023-1601-y

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Received: 28 May 2021
Accepted: 24 December 2023
Published: 25 January 2024
© Institute of Computing Technology, Chinese Academy of Sciences 2024
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